The present invention relates to a method for fabricating a semiconductor device, and more specifically a semiconductor device including contact: holes in alignment with a base pattern and a method for fabricating the same.
As LSIs become larger-scaled, more micronization of devices is pursued.
To realize semiconductor integrated circuits including gates, interconnections and contact holes of more micronized dimensions, conventionally wavelengths of the exposure radiation for the photolithography have been made shorter to thereby improve resolving power.
While minimum resolved dimensions have been thus diminished, various device structures which decrease margins for alignment between lithography steps have been studied. In place of diminishing dimensions of patterns to be formed, dimensions of devices have been decreased.
As such structure, self-aligned contact (hereinafter called SAC), for example, is known.
The conventional SAC structure will be explained in comparison with a case including no SAC structure.
As shown in FIG. 24A, in a case that two gate electrodes 208 are formed on a silicon substrate 200, and an inter-layer insulation film 226 is formed on the gate electrodes 208, when a contact hole 228 is opened between the two gate electrodes 208 down to the silicon substrate 200, the gate electrodes 208 must be arranged, considering in advance alignment precision for opening the contact hole 228.
That is, gaps (a) between the contact hole 228 and the gate electrodes 208, which are larger than an alignment precision must be ensured so that when a conducting film is buried in the contact hole 228, the conducting film does not short-circuit with the gate electrodes 208 (FIG. 24B). Accordingly, a gap between the gate electrodes 208 is subject to the contact hole, which hinders further micronization.
In contrast to this, as shown in FIG. 24C, gate electrodes 208 are covered with an insulation film 230 having etching selectivity with the inter-layer insulation film 226. The insulation film 230 functions as an etching stopper in etching the inter-layer insulation film 226 to thereby protect the insulation film 232 (on the gate electrodes 208 and on the side walls) from excessive etching, so that the gate electrodes 208 are never exposed in the opening 228 by over-etching of the insulation film 232. Accordingly, a conducting film buried in the contact hole 228 is not short-circuited with the gate electrodes 208.
Thus, when disalignment occurs in the lithography step of forming the contact hole 228, an opening down to a silicon substrate 200, is defined only by the gate electrodes 208 and the insulation film 230, and even when the contact hole 228 is a little disaligned with the gate electrodes 208, the opening can be formed in a prescribed position (FIG. 24D). This enables the device to be micronized.
A method for fabricating the conventional semiconductor device including the SAC structure will be specifically explained by means of a structure of the cell array region of a DRAM with reference to FIGS. 25 and 26.
First, a device isolation film 202 is formed on a silicon substrate 200 by, e.g., the usual LOCOS method.
Then a gate insulation film 206 is formed in a device region 204 by, e.g., thermal oxidation.
Subsequently gate electrodes 208 are formed on the gate insulation film 206. Insulation films of, e.g., doped polycrystalline silicon film and silicon oxide film are continuously deposited by CVD, and the laid films are processed in the same pattern, and the gate electrodes 208 having the top surfaces covered with an insulation film 210 are formed (FIG. 25A).
Then, ions are implanted with the gate electrodes 208 as a mask to form in the device region an impurity-doped region 212 which is to be a low-concentration diffused layer of LDD structure.
Next, an insulation film 214 of, e.g., silicon oxide film is deposited on the entire surface (FIG. 25B).
Subsequently, the insulation film 214 is etched back by anisotropic etching to form sidewall insulation films 216 on the side walls of the gate electrodes 208.
Subsequently, ions are implanted with the gate electrodes and the sidewall insulation films as a mask to form an impurity doped region 218 which is to be a high-concentration diffused layer of LDD structure (FIG. 25C).
Then, the implanted impurity is activated by, e.g., a thermal treatment at 1000xc2x0 C. for 10 seconds to form a source/drain diffused layers 220, 222 of LDD structure.
Then, an etching stopper film 224 of, e.g., silicon nitride film is deposited. The etching stopper film 224 is to be a protection film for protecting the base from being etched off when contact holes are opened in an inter-layer insulation film to be deposited on the etching stopper film 224.
Subsequently, an insulation film of, e.g., silicon oxide film is deposited and has the surface polished by, e.g., CMP (Chemical Mechanical Polishing) to form an inter-layer insulation film 226 having the surface planarized (FIG. 26A). The inter-layer insulation film 226 is formed of a material providing an etching selectivity with respect to the etching stopper film 224.
Subsequently, contact holes 228 opened on the source/drain diffused layers 220, 222 are formed.
When the contact holes 228 are etched, the inter-layer insulation film 226 is etched under conditions for etching the silicon oxide film, which can provide a sufficient selective ratio with respect to silicon nitride film, whereby even when parts of the contact holes 228 are extended over the gate electrodes 208, the etching stopper film 224 is not substantially etched.
Thus, the sidewall insulation films 216, and the insulation film 210 on the gate electrodes 208 are not excessively etched, and the contact holes can be stably opened.
Then, the etching stopper film 224 is etched to expose the source/drain diffused layers 220, 222 in the contact holes 228 (FIG. 26C).
In etching the etching stopper film 224 it is usual that anisotropic etching is not used, but wet etching in which the etching isotropically goes on is used. There are two reasons for this. One of the reasons is that the etching stopper film remaining as the sidewall insulation films narrow the contact regions, which increases contact resistance. The other of the reasons is to prevent the silicon substrate from being damaged by the anisotropic etching and having crystal defects.
The contact holes 228 are thus opened, whereby regions where the contact holes 228 are formed can overlap the gate electrodes 208, so that even when a resist pattern is a little disaligned by disalignment in the lithography step, the contact holes 228 can be opened in alignment with the gate electrodes 208 or the device isolation film 202.
As LSIs are higher integrated, new problems of the method for fabricating the above-described conventional semiconductor device have been made clear.
To attain higher integration of a semiconductor device it is necessary to form a larger number of transistors in a smaller region. The gap between the gate electrodes 208 is made smaller. In DRAMs, for example, the pattern size is about 0.7 times every generation, and is diminished by about xc2xd in two generations. On the other hand, to sufficiently function the etching stopper film 224 in the method for fabricating the semiconductor device shown in FIGS. 25 and 26, substantially the same film thickness as in the conventional semiconductor device is required.
When a semiconductor device is fabricated with these conditions satisfied, the contact region between the gate electrodes 208 is completely filled with the etching stopper film 224 (FIG. 27).
Here, to form the contact hole 228 in the contact region between the gate electrodes 208 it is necessary to remove the etching stopper film 224 filled in the contact region, but it is very difficult to remove the etching stopper film 224 in the contact region.
That is, to remove the etching stopper film buried in the contact region by the above-described wet etching, the etching stopper film has to be etched off by a film thickness corresponding to a height of the gate electrodes 208, but the etching stopper film below the inter-layer insulation film is also side-etched by substantially the same degree. Consequently, for example, the etching stopper film 224 on the gate electrodes 208 is completely etched, and a micronized pattern formed on the inter-layer insulation film 226 is often broken.
In removing the etching stopper film 224 by anisotropic etching, because an etching selectivity usable in wet etching cannot be ensured, the etching is carried on after the etching stopper film 224 on the side walls 216 is removed, to remove the etching stopper film 224 between the gate electrodes 208, and the sidewall insulation films 216 decrease a film thickness to expose, in some cases, the gate electrodes 208 in the contact hole 228. When the gate electrodes 208 are exposed in the contact hole 228, the gate electrodes 208 short-circuit with the source/drain diffused layers 220, 222, and the transistors often do not normally operate.
Also in completely etching off the etching stopper film of a height of the gate electrodes, to completely remove the etching stopper film it is necessary to a little over-etch in consideration of a disuniform film thickness of the inter-layer insulation film (a height of the gate electrodes), a disuniform etching amount, etc. This excessive etching amount is substantially proportional to a thickness of the insulation film. In a case that the etching stopper film is buried deep, the over-etching amount is accordingly increased. Accordingly in the conventional method the silicon substrate is unavoidably much damaged.
An object of the present invention is to provide a method for fabricating a semiconductor device relating to a contact hole opening technique and is suitable for further micronization of a semiconductor device.
The above-described object is achieved by the semiconductor device comprising: a semiconductor substrate; a device region defined by a device isolation film formed on the semiconductor substrate; a fist interconnection formed on the device region; an insulation film covering an upper surface and side walls of the first interconnection; an inter-layer insulation film formed on the semiconductor substrate with the insulation film formed on, and having an opening formed in a region including the device region; and a second interconnection formed, extended on the inter-layer insulation film and/or the insulation film, and connected to the device region in the opening. The semiconductor device of this structure facilitates forming micronized openings by loose rules for the lithography step.
In the above-described semiconductor device it is preferable that a plurality of the first interconnection are extended on the device region, and the second interconnection is connected to the device region between the first interconnections.
In the above-described semiconductor device it is preferable that the insulation film and the inter-layer insulation film have height substantially equal to each other, and the second interconnection is buried between the inter-layer insulation film and/or the insulation film.
The above-described object is achieved by a method for fabricating a semiconductor device comprising: a first interconnection forming step of forming a first interconnection having an upper surface covered with a first insulation film on a base substrate; an insulation film depositing step of sequentially depositing a second insulation film and a third insulation film on the base substrate with the first interconnection formed on; an opening forming step of etching the third insulation film with the second insulation film as a stopper to form an opening in a first region containing a region where the first interconnection is formed; and a contact hole forming step of etching the second insulation film in the opening to form sidewall insulation films of the second insulation film on the side walls of the first interconnection and form by self-alignment with the first interconnection a contact hole to be connected to the base substrate. According to the method for fabricating a semiconductor device, the second insulation film to be the etching stopper film is also the insulation film for the sidewall insulation films, which prevents the contact region for the gate electrodes from being filled with the second insulation film even in a case that the gate electrodes are spaced by a narrow gap.
According to the conventional method for fabricating a semiconductor device, two sidewall insulation films are formed between gate electrodes, and an etching stopper film is further formed on the side walls of the sidewall insulation films. To form an opening between gate electrodes, it is necessary to set an interval between the gate electrodes in consideration of their thickness, and an interval of at least a sidewall widthxc3x972+an etching stopper film thicknessxc3x972+xcex1 (contact size) must be ensured. However, according to the above-described method of the present application a width of twice an etching stopper film thickness (or twice a sidewall thickness) can be decreased. That is, the interval between the gate electrodes can be reduced to a sidewall widthxc3x972 (or an etching stopper film thicknessxc3x972)+xcex1. Thus, the opening has an interior space allowance, which facilitates forming an opening of a narrow opening width.
A film forming the sidewall insulation films is the etching stopper film, which can decrease film forming steps and etching steps. This results in a shorter process and lower costs.
In the above-described method for fabricating a semiconductor device it is preferable that in the opening forming step, the opening bridges both regions on both side of the first interconnection, whereby it is not necessary to leave a micronized pattern on the gate electrodes, which enables rules for the lithography step to be loosened. The first opening formed over both sides of the first interconnection is divided into two or more smaller openings on the first interconnection. Thus smaller openings than drawing rules for forming an opening bridging regions both sides of the first interconnection can be formed without disalignment.
In the above-described method for fabricating a semiconductor device, it is preferable that the method further comprises, after the insulation film depositing step, an insulation film removing step of retreating a surface of the third insulation film to expose a part of the second insulation film on the first interconnection, whereby an opening bridging regions on both sides of the first interconnection is divided by the first interconnection, and two or more openings can be formed.
In the method for fabricating a semiconductor device, it is preferable that the method further comprises, after the contact hole forming step, a second interconnection forming step of forming a second interconnection buried in the opening and connected to the base substrate, whereby two or more interconnections connected to the base substrate through an opening and divided by the first interconnection can be formed.
In the above-described method for fabricating a semiconductor device it is preferable that in the second interconnection forming step, the second interconnection which contains an impurity, which donates to electric conductivity of the base substrate, is formed and the impurity dopes into the base substrate by diffusion from the second interconnection, whereby a shallow diffused layer can be easily formed directly below the second interconnection.
In the above-described method for fabricating a semiconductor device it is preferable that the method further comprises, prior to the first interconnection forming step, a device isolation film forming step of forming a device isolation film on the base substrate; and a device isolation film removing step of removing the device isolation film until a surface of a device region defined by the device isolation film has a height substantially equal to the device isolation film, whereby the second interconnection can be formed by self-alignment without being influenced by steps of the device isolation film.
In the above-described method for fabricating a semiconductor device it is preferable that the method further comprises, prior to the first interconnection forming step, a device isolation film forming step of forming a device isolation film on the base substrate; a first conducting film depositing step of depositing a first conducting film on the base substrate with the device isolation film formed on; and a conducting film burying step of polishing a surface of the base substrate with the first conducting film formed on until the device isolation film is exposed to bury the first conducting film in the device region defined by the device isolation film and planarize a surface of the base substrate, and wherein in the first interconnection forming step, the first conducting film under the first interconnection is processed in the substantially same pattern as the first interconnection, whereby steps of the device isolation film can be buried with the first conducting film, which enable the second interconnection to be formed by self-alignment without being influenced by the steps of the device isolation film.
In the method for fabricating a semiconductor device it is preferable that the method further comprises, prior to the first interconnection forming step, a device isolating step of forming a device isolation film on the base substrate, and wherein in the first interconnection forming step, the first interconnection is formed on the device region defined by the device isolation film and on the device isolation film; and in the insulation film removing step, the third insulation film is retreated until the second insulation film formed on the first interconnection on the device region is exposed, whereby the second interconnections can be formed by self-alignment without being influenced by steps of the device isolation film. That is, cavities formed by steps of the device isolation film do not interconnect the second interconnections, and the second interconnections divided by the first interconnections can be formed.
The above-described object is achieved by a method for fabricating a semiconductor device comprising: a device isolation film forming step of forming a device isolation film on a semiconductor substrate to define a plurality of device regions extended in a first direction and arranged in a staggered layout; a word line forming step of forming a plurality of word lines having surfaces covered with a first insulation film and extended in a second direction intersecting the first direction, two of the word lines being extended in each of the device regions; an insulation film depositing step of depositing a second insulation film on the semiconductor substrate with the word lines formed on; a resist pattern forming step of forming a resist pattern for covering regions which are between the device regions extended in the first direction and are between the two word lines intersecting the respective device regions and the word lines which are adjacent to the two word lines on the outsides of the two word lines, on the second insulation film on one sides of the respective device regions; and an opening forming step of etching the second insulation film with the resist pattern as a mask to form first openings extended from the respective device regions between the two word lines intersecting the respective device regions to the other sides of the respective device region, and second opening opened on the respective device regions between the adjacent word lines intersecting the different device regions. According to the method for fabricating a semiconductor device, the lithography step for opening the contact holes for leading the bit lines and the contact holes for leading the storage electrodes can have loosened rules.
In the above-described method for fabricating a semiconductor device it is preferable that the method further comprises a contact hole forming step of etching the first insulation film in the first openings and the second openings to form sidewall insulation films of the first insulation film on side walls of the word lines and contact holes connected to the semiconductor substrate by alignment with the word lines, whereby the openings for the contact holes for leading the bit lines from the semiconductor substrate, and the openings for the contact holes for leading the storage electrodes from the semiconductor substrate can be easily formed.
The above-described object can be achieved by a method for fabricating a semiconductor device comprising: a device isolation film forming step of forming a device isolation film on a semiconductor substrate to define a plurality of device regions extended in a first direction and arranged in a staggered layout; a word line forming step of forming a plurality of word lines having surfaces covered with a first insulation film and extended in a second direction intersecting the first direction, two of the word lines being extended in each of the device regions; an insulation film depositing step of depositing a second insulation film and a third insulation film on the semiconductor substrate with the word lines formed on; a planarization step of planarizing the third insulation film; a resist pattern forming step of forming a resist pattern for covering regions which are between the device regions extended in the first direction and are between the two word lines intersecting the respective device regions and the word lines which are adjacent to the two word lines on the outsides of the two word lines, on the third insulation film and on one sides of the respective device regions; an opening forming step of etching the third insulation film with the resist pattern as a mask to form first openings extended from the respective device regions between the two word lines to the other sides of the respective device regions, and second openings opened on the device regions between the adjacent word lines intersecting the different device regions; and a contact hole forming step of etching the second insulation film in the first openings and the second openings to form sidewall insulation films of the second insulation film on side walls of the word lines and to form contact holes to be connected to the semiconductor substrate in alignment with the word lines. According to the method for fabricating a semiconductor device, the openings for the contact holes for leading the bit lines from the semiconductor substrate, and the openings for the contact holes for leading the storage electrodes from the semiconductor substrate can be easily formed. The lithography for opening the contact holes does not require transferring a micronized contact hole pattern, which can simplify the lithography.
The above-described object is achieved by a method for fabricating a semiconductor device comprising: a word line forming step of forming a plurality of word lines extended in a first direction on a semiconductor substrate; a bit line forming step of forming a plurality of bit lines having upper surfaces covered with a first insulation film and extended in a second direction intersecting the first direction on the semiconductor substrate with the word lines formed on; an insulation film depositing step of depositing a second insulation film and a third insulation film on the semiconductor substrate with the bit lines formed on; a planarization step of planarizing a surface of the third insulation film; a resist pattern forming step of forming a striped resist pattern for alternately covering regions between the word lines on the planarized third insulation film; an opening forming step of etching the third insulation film with the resist pattern as a mask to open a plurality of openings in regions between the bit lines; and a contact hole forming step of etching the second insulation film in the openings to form side walls of the second insulation film on side walls of the bit lines and open contact holes to be connected to the semiconductor substrate in alignment with the bit lines. According to the method for fabricating a semiconductor device, the opening for the contact holes for leading the storage electrodes from the semiconductor substrate can be easily formed. The lithography for opening the contact holes does not require transferring a micronized contact hole pattern, which can simplify the lithography.